How to enable CLK_OUT_A on A20 port I pin 12 connector 4-27

[engidea]

Dear Olimex

I would like to output a 6MHz clock on the above port and as far as I understand it should be possible.
The documentation on the FEX is quite long and I cannot find a reference on how to do the above.

A solution would be good, actually great !

If there is nothing ready for the above could you point out to some documentation ?
I have looked at
https://www.olimex.com/wiki/How_to_edit_board_configurations_and_definitions_in_the_official_Debian_Linux
http://linux-sunxi.org/GPIO
http://linux-sunxi.org/Talk:Fex_Guide

Thanks, Damiano

[dannym]

I would like to output a 6MHz clock on the above port and as far as I understand it should be possible.
The documentation on the FEX is quite long and I cannot find a reference on how to do the above.

In Linux 4.3, have a driver get the clock "clk_out_a" using clk_get. Technically, for this, the device that needs the clock needs to be in the device tree (dts) file. But for the quick and dirty way see below.

No idea how it works on older kernels.

struct clk* clk1;
unsigned long rounded_rate;
clk1 = clk_get(NULL, "clk_out_a");
rounded_rate = clk_round_rate(clk1, 600000000U);
ret = clk_set_rate(clk, rounded_rate);

[engidea]

There is a "discussion" on sunxy group that is quite extensive

https://groups.google.com/forum/#!topic/linux-sunxi/zDOxAP_JJIc

Long story short, you also need a pullup...