RGMII clock delay

[VI]

I looking inside the PCB and see the RGMII_RX_CLK and TX_CLK are some PCB skew.
As I know about length matching signal in this interface, I interesting to know the calculation for designing this connection?
Can anybody help me with it?

[LubOlimex]

It can have some fluctuation, the chip has registers for Pad Skew, so you can fix small differences in length by software means. Refer to the datasheet of the Ethernet controller, and more specifically page 23: https://datasheet.lcsc.com/szlcsc/KSZ9031RNXCA_C58758.pdf

You can see the skew that we use with KSZ9031 in this part of the Linux code: https://github.com/OLIMEX/OLINUXINO/blob/master/SOFTWARE/A20/A20-build-3.4.103-release-7/a20-phy_1000_100-dram.patch

Edit: Linux skew