ESP8266 Flash SQI Mismatch

[nmap]

I'm working from MOD-WIFI-ESP8266 as a reference design. I do not understand why the SQI pins to the serial flash U2 are mismatched... D0 goes to IO1, D1 goes to IO0, D3 goes to IO2, D2 goes to IO3. See attached.

Any explanation from the Olimex engineers or other knowledgeable folks would be appreciated.

[JohnS]

It'll be a simpler board layout.

It doesn't matter which bit is written to where since it will also be read back from wherever it was.

John (it fooled me too... a while ago... non-Olimex)

[MBR]

Yes, JohnS is right, I'm now looking at the board in the EAGLE and it looks that the "mismatching" was used to connect the Flash memory without adding more layers and keeping price low. But maybe with more creative design, it could be possible to connect them straight without any ill effects (I tried to, just for fun, and it requires four vias and to shring a bit the ground polynoms under the Flash package).