verilog - FPGA_LED on gatemate

[sures]

Hi,
I have 3 different 8 leds arrays connected physically to my gatemate board:
https://github.com/rugosi/olimex_gatemate_evb/raw/main/images/8leds.webp
https://github.com/rugosi/olimex_gatemate_evb/raw/main/images/PMOD_LEDx8.jpg
https://github.com/rugosi/olimex_gatemate_evb/raw/main/images/rgbleds_with_schema.webp

The definition of the connections is the following:

Code Select Expand

## ##################################################
## GPIO Led 8 led array on bank NA (Optional)
## ##################################################
Pin_out   "RED_LEDS[0]"   Loc = "IO_NA_A0";
Pin_out   "RED_LEDS[1]"   Loc = "IO_NA_A1";
Pin_out   "RED_LEDS[2]"   Loc = "IO_NA_A2";
Pin_out   "RED_LEDS[3]"   Loc = "IO_NA_A3";
Pin_out   "RED_LEDS[4]"   Loc = "IO_NA_A4";
Pin_out   "RED_LEDS[5]"   Loc = "IO_NA_A5";
Pin_out   "RED_LEDS[6]"   Loc = "IO_NA_A6";
Pin_out   "RED_LEDS[7]"   Loc = "IO_NA_A7";

## ##################################################
## GPIO Led 8 led array on PMOD (Optional)
## ##################################################
Pin_out   "PMOD_LEDS[0]"   Loc = "IO_EA_B7";
Pin_out   "PMOD_LEDS[1]"   Loc = "IO_EA_A7";
Pin_out   "PMOD_LEDS[2]"   Loc = "IO_EA_B6";
Pin_out   "PMOD_LEDS[3]"   Loc = "IO_EA_A6";
Pin_out   "PMOD_LEDS[4]"   Loc = "IO_EA_B5";
Pin_out   "PMOD_LEDS[5]"   Loc = "IO_EA_A5";
Pin_out   "PMOD_LEDS[6]"   Loc = "IO_EA_B4";
Pin_out   "PMOD_LEDS[7]"   Loc = "IO_EA_A4";

## ##################################################
## GPIO Led 8 rgb led array on bank NB (Optional)
## ##################################################
Pin_out   "RGB_LEDS[0]"   Loc = "IO_NB_A0";
Pin_out   "RGB_LEDS[1]"   Loc = "IO_NB_A1";
Pin_out   "RGB_LEDS[2]"   Loc = "IO_NB_A2";
Pin_out   "RGB_LEDS[3]"   Loc = "IO_NB_A3";
Pin_out   "RGB_LEDS[4]"   Loc = "IO_NB_A4";
Pin_out   "RGB_LEDS[5]"   Loc = "IO_NB_A5";
Pin_out   "RGB_LEDS[6]"   Loc = "IO_NB_A6";
Pin_out   "RGB_LEDS[7]"   Loc = "IO_NB_A7";
Pin_out    "RGB_R"         Loc = "IO_NB_B0";
Pin_out    "RGB_B"         Loc = "IO_NB_B1";
Pin_out    "RGB_G"         Loc = "IO_NB_B2";

I also defined the fpga led in my ccf file:

Code Select Expand

Net   "LED"        Loc = "IO_SB_B6";


-------------------------
The enriched blink verilog file, based on the colognechip demo, is the following:
`timescale 1ns / 1ps

Code Select Expand

module blink(
input wire CLK,
input wire RESET,
output wire LED, // pmod blinks 2 or 5
output wire [7:0] RED_LEDS
);

reg [26:0] counter;
    reg [7:0] sum = 8'b11111111;

wire clk270, clk180, clk90, clk0, usr_ref_out;
wire usr_pll_lock_stdy, usr_pll_lock;

CC_PLL #(
.REF_CLK(10.0),      // reference input in MHz
.OUT_CLK(100.0),     // pll output frequency in MHz
.PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED
.LOW_JITTER(1),      // 0: disable, 1: enable low jitter mode
.CI_FILTER_CONST(2), // optional CI filter constant
.CP_FILTER_CONST(4)  // optional CP filter constant
) pll_inst (
.CLK_REF(CLK), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0),
.USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy), .USR_PLL_LOCKED(usr_pll_lock),
.CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(clk0), .CLK_REF_OUT(usr_ref_out)
);

assign LED = counter[26];

assign RED_LEDS = sum;

always @(posedge clk0)
begin
if (!RESET) begin
counter <= 0;
end else begin
counter <= counter + 1'b1;
end

        if ( &counter[22:0] ) begin
            sum <= sum - 1;
        end

end

endmodule



It compiles just fine, but the FPGA_LED is not blinking, but the 3rd led on the pmod module. The red led series blinks just fine.

The PMOD and rgb led modules are not present in the module, just the fpga_led and the red_leds, but physically, they are present and connected via wires.

If I change the "LED" name to "led" in the .ccf and the .v file (3 occurences), there is no blinking at all.

Tried to read the schema to find out how pin IO_SB_B6 is related to IO_EA_B6 or IO_EA_A5, but found nothing.

I am sure I made some serious mistake, but don't know what.

I am using the 01.09.2024 revision of colognechip gatemate, with a hand compiled openFPGALoader for a debian bookworm system.

[sures]

With removing reg_leds from the .v source code, the fpga_led blinks correctly.

[sures]

Or if a module is connected physically, I have to assign a state to it in order to make it deterministic?

[LubOlimex]

Tried to read the schema to find out how pin IO_SB_B6 is related to IO_EA_B6 or IO_EA_A5, but found nothing.

Umm, is there IO_EA_B6 or IO_EA_A5 in the schematic at all?

[sures]

Maybe I misunderstand:

on the schema, there is a block called IO East which has a mention EA_A5 <-> J16 <-> IO_EA_A5 which is connected via Ext-bus to the UEXT & PMOD Connectors block which has an input EA_A5 connected to the pin 4 (A3) which is connected to the pin 3 of the module Pmod1.

Idem for the other port.
I am using GateMateA1-EVB_Rev_A.pdf schematic.
I supposed to access this way the pmod1 via the ports
 EA_A4
  EA_B4
   EA_A5
   EA_B5
   EA_A6
   EA_B6
   EA_A7
   EA_B7
 

[LubOlimex]

Pin 4 of U4 is connected to pin #2 of Pmod1 (not 3).

[sures]

Yes, that is true, I overlooked, however, in the .ccf I think I identified the pin correctly.

Back to my main problem: why the fpga_led does not blink if devices are connected to the other banks/ pmod ports? An instead of the fpga_led, one of the pmod leds blinks?

Tried also with Pin_out instead of Net, no success...

[LubOlimex]

in_out  "led"  Loc = "IO_SB_B6";

Looking at our ccf in the test it contains only the following:

# cc-pll.ccf 15.2.24/16.2.24 2nd & 3rd ver PDR
Pin_in "CLK0" Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;  #10MHz osc
Pin_out "locked" Loc = "IO_EB_A0";  #CCEVB J2 pin 33, Oli BANK_EB1 pin 19

Pin_out "CCEVB_LED" Loc = "IO_EB_B1";  #Oli BANK_EB1 pin 18
Pin_out "OLIMEX_LED" Loc = "IO_SB_B6";  #CCEVB J10 pin 18