Stackup thickness - iMX8 SOM?

[cushychicken]

Can Olimex provide any guidance on the stackup used for the iMX8MP SOM?

I looked at the stackup provided in your PCB's Physical Stackup panel in Kicad, and that reports this stackup:

https://imgur.com/a/lQfHDLk

However, I note that this totals up to a 1mm thickness, and I measure a SOM board thickness of 1.6mm with calipers.

Asking because I reused this layout and I'm getting some odd behavior out of the DRAM, and I'm trying to see if I can rule out my stackup as the source of the issues. (So far, I have not been able to rule it out - it may be the cause of my problems here.)

If you have a stackup table or trace geometry table that you can share that's separate from Kicad, I'd be super grateful.

Thank you!

[LubOlimex]

Thanks for notice, it is probably left over from old board. We will fix it for next release of the design files. It is 1.6mm indeed.

TOP 1oz (0.035mm)
Prepreg 1080*1 0.075mm
PWR Hoz(0.018mm)
Prepreg 2116*1 0.115mm
LN3 Hoz(0.018mm)
Adjust Core 1.065mm
LN4 Hoz(0.018mm)
Prepreg 2116*1 0.115mm
GND Hoz(0.018mm)
Prepreg 1080*1 0.075mm
BOT 1oz (0.035mm)

TOTAL: 1.6mm

[LubOlimex]

Upon investigating further it turns out the KiCAD version used to create the design is KiCAD version 5.1.4 (the KiCAD from your picture is quite newer) - old KiCAD had only total thickness, there is no per layer thickness. The version of the KiCAD used is visible in the page info at the bottom right of the PDF exports. To avoid problems upon conversation it is highly suggested to use the same KiCAD version for this design (aka KiCAD 5.1.4)

[cushychicken]

Yeah, I figured that these values were populated as defaults when loaded in the newer version of Kicad. I did not populate the values you see in the picture.

Is this stackup table documented anywhere? Do you have an impedance geometry table with target impedances for all traces in the system?

Asking because I calculated a separate stackup than the one you're using, and I'm thinking I introduced an issue somewhere - my DRAM is not able to run at full speed.

[LubOlimex]

We don't have a table suitable for publishing and it will require further effort to make it presentable. But such a table is not really needed since all lengths can be measured from the sources.

I don't think the DRAM in our board is running at max speed either. Have to check the sources.

For RAM related issues it is good idea to also check the iMX forums and maybe use the iMX DDR tool: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467

[cushychicken]

We don't have a table suitable for publishing and it will require further effort to make it presentable.

One of the nice things about newer KiCAD versions is that they include tools for making tables like this easily. I imported your design into KiCAD v8 and made the following stackup on the Comments layer:

https://imgur.com/a/olimex-som-stackup-3W0OvNh

If you are able to share an email address with me privately, I would be happy to share the PDF version of this for you to add to your official documentation.

But such a table is not really needed since all lengths can be measured from the sources.

Uh... I don't really understand this comment. Part of why I needed to ask in the first place is that your DRAM breakout has multiple trace geometries in it - 3.2mil for the SOC fanout, then 5 mil for the meander to the DRAM. It was hard for me to know which one was your target geometry without a trace impedance table.

I am working on making a Trace Impedance Table separately to compare your target impedances against the ones I used.

I don't think the DRAM in our board is running at max speed either. Have to check the sources. Family-DDR-Tool-Release/ta-p/1104467

Thanks for sharing that! We started our build off of the last stable mainline buildroot version, which had DRAM speed pegged to 2000MHz. This was failing to configure and had extra tight eye margins, and failed many basic write/readback tests. Turning down the speed to 1600MHz helped us get to stable operating conditions. I'd be curious to know your operating bus speed - I am trying to eliminate a few possible sources of error on my end.

For RAM related issues it is good idea to also check the iMX forums and maybe use the iMX DDR tool: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467

I'm so glad you pointed that out! This is the tool I'm using to check our own boards. Are you able to share any information on how to run this on the iMX8MP SOM + EVB?

I was able to run it on our custom boards by reworking a USB cable into a bus that I cut the endpoint to. I am not having much success with getting the DDR tool to run on the Olimex SOM. I tried reworking in to USB1 several times, but that did not work. (All attempts used the iMX8M in serial downloader mode.)

I'm going to try again today with some USB A to USB A cables I got from Amazon. I'll let you know how it goes. If you have any hints or ideas of what I may be getting wrong, I'm all ears for getting it working.

Finally - thank you so much for releasing this board design to the world. I have worked with many iMX series chips in my career, and it's a real delight to get to work with one in KiCAD, which is by far my favorite CAD package. Much love for Olimex.   

[LubOlimex]

From my experience with RAM memories and Linux-enabled boards - it is not something set in stone, you might calculate but you can also empirically test with different frequency and timings. Just make sure to run long memory stress tests to ensure the settings you've entered are stable.

Also if you have to change the memory in future (due to unavailability, price gouging, etc), it is quite likely these settings would need to be changed again even if you find a memory with the same properties. There is always some difference in behavior when you change the RAM.

If you are able to share an email address with me privately, I would be happy to share the PDF version of this for you to add to your official documentation.

You can use support@olimex.com

Uh... I don't really understand this comment. Part of why I needed to ask in the first place is that your DRAM breakout has multiple trace geometries in it - 3.2mil for the SOC fanout, then 5 mil for the meander to the DRAM. It was hard for me to know which one was your target geometry without a trace impedance table.

I am working on making a Trace Impedance Table separately to compare your target impedances against the ones I used.

It is just something we don't have currently ready for sharing and will require extra work, and our team is busy with other projects. Basically what you have to do to measure, someone here has to do the same to confirm the values during designing the board. I will add it in our TODO list and it will probably get published in future just don't expect it asap.

I'm so glad you pointed that out! This is the tool I'm using to check our own boards. Are you able to share any information on how to run this on the iMX8MP SOM + EVB?

I can't remember if we ever used the tool for testing mainly for calculations, for RAM testing we used memtester (it is the tool available after building the image and doesn't require anything else). So if you managed to get it working on the Olimex board it will be very helpful for others if you can share how you get it working exactly.